1. Field of the Invention
The present application generally relates to a memory cell and, more particularly, to a capacitor-less dynamic random access memory (DRAM) cells.
2. Description of the Prior Art
A known dynamic random access memory (DRAM) cell includes a transistor and a capacitor. The transistor functions as a switch controlling whether a data is being written into, read from, or held in the DRAM cell. The capacitor functions as the storage device. This one-transistor/one-capacitor (1T/1C) structure limits the extent to which the DRAM cell can be miniaturized and hence the memory capacity of the DRAM device given a certain physical size. The increasing need for smaller electronic systems and larger memory capacity, among other reasons, requires reduction in size of the physical structures inside a memory device.
Therefore, a capacitor-less DRAM cell has been made to further reduce the size of the DRAM cell. A capacitor-less DRAM includes a metal-oxide semiconductor field-effect transistor (MOSFET) on a silicon-on-insulator (SOI) wafer. This new memory cell uses a floating body of a MOSFET on silicon-on-insulator as a storage node. Therefore, the capacitor-less DRAM cell may not need a complicated storage capacitor, which means that the capacitor-less DRAM cell may have a smaller size than that of the 1T/1C DRAM cell. However, it may be desirable to provide good memory data retention and prevent junction leakage for the capacitor-less DRAM cell.